PIC16C711-20/SO【PDF 32/177 页】IC MCU OTP 1KX14 A/D 18SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3861

28页 29页 30页 31页 [32页]33页 34页 35页 36页

127

7593L–AVR–09/12

AT90USB64/128

non-PWM modes refer to Table 15-1 on page 137. For fast PWM mode refer to Table 15-2 on

page 137, and for phase correct and phase and frequency correct PWM refer to Table 15-3 on

page 138.

A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOCnx strobe bits.

15.8

Modes of operation

The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,

is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Out-

put mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare

match (see “Compare Match Output unit” on page 126).

For detailed timing information refer to “Timer/Counter timing diagrams” on page 134.

15.8.1

Normal mode

The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in

the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the Normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum

interval between the external events must not exceed the resolution of the counter. If the interval

between events are too long, the timer overflow interrupt or the prescaler must be used to

extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the

Output Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

15.8.2

Clear Timer on Compare Match (CTC) mode

In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register

are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =

12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This

mode allows greater control of the compare match output frequency. It also simplifies the opera-

tion of counting external events.

The timing diagram for the CTC mode is shown in Figure 15-6 on page 128. The counter value

(TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter

(TCNTn) is cleared.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式